Programmable logic devices (PLDs) are a type of integrated circuit that enable the downloading of configuration bits to implement a user's circuit designs. PLDs include various memory elements, as will be described in more detail below. Configuration random access memory (CRAM), including configurable logic element memory (CLEM) are subject to upset from cosmic neutrons, thermal neutrons and terrestrial alpha particles. The failure rate associated with this is commonly known as Soft Error Rate (SER). The industrial metric used to quantify the SER of the circuit is known as FIT rate or FIT/Mb when normalized to device's size. SEU enhanced solutions are used to reduce SEU upsets in CLEM elements. Multi-bit upsets (MBUs) are events in which two or more error bits occur in the same word. With the adequate interleaving strategy and ECC scheme they are expected to be correctable.
In an ASIC or FPGA, a single ion strike may cause one or more voltage pulses/glitches to propagate through the circuit. The glitches are called single-event transients (SETs). If a SET propagates through the logic and induces a corrupted logic state to be latched in a memory cell, the SET is then considered an SEU and can results in an increase of the integrated circuit or FPGA FIT rate. SETs in a shift register latch (SRL) clock circuit have been identified as a source of abnormally large MBUs in CLEM logic by allowing erroneous data to be latched in given lookup table RAM (LUTRAM) arrays. These SET induced MBUs are larger than the cell interleaving size and therefore are uncorrectable. SETs in CLEM elements increase the FPGA FIT rate and force the user to reconfigure the FPGA.